The invention relates to a method of reducing lithographic image size for integrated circuit (IC) manufacture. More particularly, it is a method of forming a mask having openings of a size smaller than obtainable by lithography.
There has been an inexorable advance in IC industry due to the insatiable appetite for scaling down the devices. Scaling device dimensions reduces cost of manufacture while increasing the performance (speed). While this advance can be attributed to new processing techniques such as replacement of wet etching by dry etching (plasma etching, reactive ion etching and ion milling), use of low-resistivity silicides and refractory metals as replacements for high-resistivity polysilicon interconnections, multiple-resists to compensate for wafer surface variations that thwart accurate fine-line lithography, laser and electron-beam processing to purify and reduce defects in materials, nonoptical methods of inspecting line widths and layer-to-layer registration to replace optical methods incapable of measuring these parameters at low-micrometer levels, lithography has been the driving force behind each step forward. Improved lithographic tools such as 1:1 optical projection systems fitted with deep-ultraviolet source and optics, electron-beam, direct-step-on-wafer, and X-ray and ion-beam systems and improved photoresist materials and processes such as multilayer resist utilizing a top resist sensitized to X-ray or electron-beam and bottom straight optical resist layer(s) are some of the components of this driving force.
Despite this tremendous progress, there remains an ever-growing need for reduction of image sizes over and beyond that offered by enhancements to lithographic tools, materials and processes, per se. However, the prior art has not been able to meet this need.
The invention precisely satisfies this need for reducing lithographic image sizes by extending lithographic resolution to smaller sizes than capable by lithography.